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In typical MP(multi-processor)-SoCs, there are several thousands of tie-off signals. These are growing as complexity and size of SoC is increasing day by day. Mutation testing is popular to find faults in the software program of software system design. There were many attempts to apply the same concept in SoC or embedded SoC testing or verification. In this(More)
  • Prokash Ghosh
  • 2016
Nowadays MP-SoCs or embedded SoCs have several hundred thousands of hard tie-off signals. Mostly, hard tie-offs signals are verified or reviewed by SoC verification team along with SoC architecture team manually. It is very cumbersome and error prone process. Often, it becomes infeasible due to large number of hard tie-offs signal in SoC. It is one of the(More)
  • Prokash Ghosh
  • 2016
Nowadays multi-core SoCs or embedded SoCs have several hundred thousands of RTL design parameters distributed across different IP instances. Ideally, we need to verify each RTL design parameter in SoC verification. It is one of the most challenging tasks of SoC verification. In this paper, we are proposing a hybrid verification methodology for parameter(More)
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