Pritha Banerjee

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Recent field-programmable gate array (FPGA) architectures are heterogeneous, owing to the presence of millions of gates in configurable logic blocks (CLBs), block RAMs, and multiplier blocks (MULs) which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithms for application-specific integrated circuits(More)
Partial reconfiguration on heterogeneous field-programmable gate arrays with millions of gates yields better utilization of its different types of resources by swapping in and out the appropriate modules of one or more applications at any instant of time. Given a schedule of sub-task instances where each instance is specified as a netlist of active modules,(More)
In this paper, we propose a placement method for islandstyle FPGAs, based on recursive bi-partitioning followed by application of space-filling curves. Experimental results of our method show 55% improvement in cost, when compared to random initial placement of the popular tool VPR. The solutions thus obtained require 44.5% fewer moves during final(More)
The increasing design complexity of modern circuits has made traditional FPGA placement techniques not efficient anymore. To improve the scalability, commercial FPGA placement tools have started migrating to analytical placement. In this paper, we propose the first academic multilevel timing-and-wirelength-driven analytical placement algorithm for FPGAs.(More)
In this paper, we propose a placement method for island-style FPGAs, based on fast yet very good initial placement followed by refinement using ultra-low temperature simulated annealing. The initial placement is the keystone of the method and the steps to obtain it are: top down coarse partitioning, allocation of partitions to regions on FPGA array,(More)
Research in VLSI placement, an NP-hard problem, has branched in two different directions. The first one employs iterative heuristics with many tunable parameters to produce a near-optimal solution but without theoretical guarantee on its quality. The other one considers placement as a graph-embedding problem and designs approximation algorithms with(More)
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for floorplanning, the traditional algorithm for ASIC do not suffice. In this paper, we have proposed an algorithm for unified floorplan topology generation and sizing for recent(More)
In this paper, two distinct approaches for fast placement onto FPGAs are proposed. In our first approach, we design a constructive heuristic for initial placement of a given netlist of CLBs on a FPGA, in order to accelerate the iterative phase of the placement in the context of re-configurable computing. The experimental results of our method show(More)
Partial Reconfiguration on heterogeneous Field Programmable Gate Arrays (FPGA) with millions of gates yields better utilization of resources by swapping in and out the active modules of one or more applications at an instant of time. Given a schedule of sub-task instances with each instance having a netlist of active modules, a global floorplanning method(More)
Recent Field Programmable Gate Arrays (FPGA) have high logic capacity and it requires fast yet high quality placement method for mapping a technology mapped netlist of a given complex digital design onto the FPGA chip. Analytical placement for FPGAs show significant scalability for large design compared to traditional simulated annealing based placement(More)