Pravin S. Mane

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The most area and power consuming arithmetic operation in high-performance circuits like Finite Impulse Response (FIR), multiplication is one. There are different types of multipliers to reducing the cost and effective parameters in FIR filter design. Among those this paper use truncated multiplier and modified Wallace multiplier in the fir design. The(More)
In nanometer regime, optimization of System-onChip (SoC) designs w.r.t. speed, power and area is a major concern for VLSI designers today. Imprecise/approximate design obviates the constraints on accuracy, stemming a novel SpeedPower-Accuracy-Area (SPAA) metrics which can pilot to tremendous improvements in speed and/or power with a feeble accord in(More)
Mapping of Intellectual Property (IP) cores onto Network-on-Chip (NoC) architectures is a key step in NoC-based designs. Energy, bandwidth, and latency are the key parameters that need to be optimized in such designs. In this paper, we propose Centralized 3-D Mapping (C3Map) using a new octahedral traversal technique and Attractive-Repulsive Particle Swarm(More)
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