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This paper deals with the design and implementation of JPEG2000 Encoder using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The new still compression image standard, JPEG2000 has emerged with a number of significant features that would allow it to be used efficiently over a wide variety of images. The scalability of the new(More)
Quantum Dot Cellular Automata is one of the six emerging technologies which help us to overcome the limitations of CMOS technology. Design of 4-bit ALU for AND, OR, XOR, and ADD operations using QCA is discussed through this paper. This design of 4-bit ALU using QCA is simple in structure having significantly lesser elements as compared to CMOS design. It(More)
Switched capacitor (SC) modulator performance is prone to various nonidealities, especially at integrator stage, which affects overall circuit performance. In this paper a set of models are proposed which takes into account SC sigma-delta (ÓÄ) modulator nonidealities, such as sampling jitter since switching circuitry is included, kT/C noise, and(More)
In the design of high speed Flash ADC selection of Thermometer to Binary decoder plays an important role. This paper describes different decoder topologies suitable for Flash ADCs. Comparative analysis between them is presented in terms of hardware required, propagation delay & power consumption. Result shows that fat tree & Mux based topologies are(More)
In this paper Flash ADC (FADC) is Implemented in 0.18 μm technology using CMOS Inverter based Threshold inverter Quantized (TIQ) comparator for effective speed and power improvement by eliminating complete resistive ladder circuit. Thermometer to binary decoder with low power consumption, less area & short critical path is selected for the design(More)
An architecture to simplify the circuit implementation of analog-to-digital (A/D) converter in a sigma-delta (S?) modulator is proposed. The two-step quantization technique is utilized to design architecture of S? modulator. The architecture is based on dividing the A/D conversion into two time steps for achieving resolution improvement without decreasing(More)
Power consumption is the major issue in VLSI design. In this paper an efficient low power first order sigma delta modulator is designed for oversampled ADC using floating gate folded cascode operational amplifier, in 0.35 µm Technology. Floating gate M OSFET have low power Dissipation hence it is an attractive solution in design of data converters, low(More)
Traditional system on chip (SOC) designs offer integrated solutions to exigent design tribulations in areas which necessitate outsized computation and restriction in certain area. Because of the common bus architecture in SOC system, performance becomes sluggish which limits the processing speed. The network on chip (NOC), due to their characteristics such(More)
Quantum Dot Cellular Automata has attracted a lot of attention due to its extremely small feature size and ultra low power consumption. It is a possible alternative for transistor based technology. This paper presents the Single Layered design and construction of Logic Generator Block which generates the logic of various devices like 1-Bit comparator, 1-(More)
Quantum Dot Cellular Automata is one of the six emerging technology which can overcome the limitations of current transistor based technology. Quantum Dot Cellular Automata is popular technology due to its extremely small feature size and ultra low power consumption. In this paper new XOR gate using Coupled Majority Voter Minority gate is proposed. Using(More)