Pravin Dakhole

Learn More
This paper deals with the design and implementation of JPEG2000 Encoder using Very High Speed Integrated Circuit Hardware Description Language (VHDL). The new still compression image standard, JPEG2000 has emerged with a number of significant features that would allow it to be used efficiently over a wide variety of images. The scalability of the new(More)
Switched capacitor (SC) modulator performance is prone to various nonidealities, especially at integrator stage, which affects overall circuit performance. In this paper a set of models are proposed which takes into account SC sigma-delta (ÓÄ) modulator nonidealities, such as sampling jitter since switching circuitry is included, kT/C noise, and(More)
In this paper Flash ADC (FADC) is Implemented in 0.18 μm technology using CMOS Inverter based Threshold inverter Quantized (TIQ) comparator for effective speed and power improvement by eliminating complete resistive ladder circuit. Thermometer to binary decoder with low power consumption, less area & short critical path is selected for the design(More)
In the design of high speed Flash ADC selection of Thermometer to Binary decoder plays an important role. This paper describes different decoder topologies suitable for Flash ADCs. Comparative analysis between them is presented in terms of hardware required, propagation delay & power consumption. Result shows that fat tree & Mux based topologies are(More)
Multiplier is a vital block in high speed Digital Signal Processing Applications. With the more advance techniques in wireless communication and high-speed ULSI techniques in recent era, the more stress in modern ULSI design under which main constraints are Power, Silicon area and delay. In all the high-speed application to Very Large Scale Integration(More)
An architecture to simplify the circuit implementation of analog-to-digital (A/D) converter in a sigma-delta (S?) modulator is proposed. The two-step quantization technique is utilized to design architecture of S? modulator. The architecture is based on dividing the A/D conversion into two time steps for achieving resolution improvement without decreasing(More)
Quantum Dot Cellular Automata is one of the six emerging technologies which help us to overcome the limitations of CMOS technology. Design of 4-bit ALU for AND, OR, XOR, and ADD operations using QCA is discussed through this paper. This design of 4-bit ALU using QCA is simple in structure having significantly lesser elements as compared to CMOS design. It(More)
This paper presents a new adaptive neural approach to improve the system performance of an Orthogonal Frequency Division Multiplexing (OFDM) based receiver structure. Peak to average power ratio (PAPR) of an OFDM signal is very large. When such a signal passes through high power amplifier, the signal gets nonlinearly distorted. This causes bit error rate(More)
Traditional system on chip (SOC) designs offer integrated solutions to exigent design tribulations in areas which necessitate outsized computation and restriction in certain area. Because of the common bus architecture in SOC system, performance becomes sluggish which limits the processing speed. The network on chip (NOC), due to their characteristics such(More)
In Analog application, multipliers plays a vital role. They are used in many fields like artificial neural networks, image processing, modulators etc. In this paper, a low power and low voltage CMOS analog multiplier is presented with performance analysis and design implementation by using Exponential Approximation circuit. In this design, MOSFETS are(More)