Praveen Raghavan

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We describe several algorithms for computing the orthogonal factorization on distributed memory multiprocessors. One of the algorithms is based on Givens rotations, two others employ column Householder transformations but with different communication schemes: broadcast and pipelined ring. A fourth algorithm is a hybrid; it uses Househlolder transformations(More)
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has been proven to be one of the most power hungry parts of the system. This paper introduces an architectural enhancement for the instruction memory to reduce energy and improve(More)
The main goals of the 2PARMA project are: the definition of a parallel programming model combining component-based and single-instruction multiple-thread approaches, instruction set virtualisation based on portable byte-code, run-time resource management policies and mechanisms as well as design space exploration methodologies for many-core computing(More)
As semiconductor manufacturing has entered into the nanoscale era, Bias Temperature Instability (BTI) -Negative BTI (NBTI) in PMOS transistors and Positive BTI (PBTI) in NMOS transistorshas become one of the most serious aging mechanisms that reduces reliability of logic gates. This paper presents a simulation-based BTI analysis in both basic (such as NAND(More)
Energy-efficient scalable soft-output signal detectors are of significant interest in emerging Multiple-Input Multiple-Output (MIMO) wireless communication systems. However, traditional high-performance MIMO detectors consume a rather high amount of power, are typically constraint to one modulation scheme and are not scalable with the number of antennas.(More)
New applications demand very high processing power when run on embedded systems. Very Long Instruction Word (VLIW) architectures have emerged as a promising alternative to provide such processing capabilities under the given energy budget. However, in this new VLIW-based architectures, the register file is a very critical contributor to the overall power(More)
Bias Temperature Instability (BTI) is posing a major reliability challenge for today's and future semiconductor devices as it degrades their performance. This paper provides a comprehensive BTI impact analysis, in terms of time-dependent degradation, of FinFET based SRAM cell. The evaluation metrics are read Static Noise Margin (SNM), hold SNM and Write(More)