Praveen Elakkumanan

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With technology scaling, combinational logic is becoming increasingly vulnerable to radiation strikes. Classical fault tolerant techniques mainly address Single Even Upsets (SEUs). Robust combinational logic designs capable of tolerating Single Event Transients (SETs) also are needed in lower technology nodes. In this paper, we present a novel SET(More)
The design of fast, low power and robust sense amplifier circuits is a challenge for nanoscale SRAMs due to the increasing bit line capacitance and process variations. Current sensing in SRAMs is promising to achieve high-speed operation in low-voltage application. In this paper, we propose a process variation tolerant, high performance and scalable current(More)
Conventional optical proximity correction (OPC) tools aim to minimize edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve. In addition, prohibitively high mask complexity is incurred, leading to(More)
Performance of system-on-chips (SoC) is limited by rising delays and noise in buses and point-to-point interconnects. This also has a profound impact on the clock distribution network. Networks-on-chip (NoC) provides a regular communication fabric that helps to overcome these limitations. However, NoCs too will face bottlenecks in clocking beyond a few GHz(More)
The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel reduced-gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in very deep(More)
The most research on the power consumption of circuits has been concentrated on the switching power and the power dissipated by the leakage current has been relatively minor area. In today’s IC design, one of the key challenges is the increase in power dissipation of the circuit which in turn shortens the service time of battery-powered electronics, reduces(More)