The design of fast, low power and robust sense amplifier circuits is a challenge for nanoscale SRAMs due to the increasing bit line capacitance and process variations. Current sensing in SRAMs is promising to achieve high-speed operation in low-voltage application. In this paper, we propose a process variation tolerant, high performance and scalable current… (More)
With technology scaling, combinational logic is becoming increasingly vulnerable to radiation strikes. Classical fault tolerant techniques mainly address Single Even Upsets (SEUs). Robust combinational logic designs capable of tolerating Single Event Transients (SETs) also are needed in lower technology nodes. In this paper, we present a novel SET… (More)
Conventional optical proximity correction (OPC) tools aim to minimize edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-k1 lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve. In addition, prohibitively high mask complexity is incurred, leading to… (More)
Performance of system-on-chips (SoC) is limited by rising delays and noise in buses and point-to-point interconnects. This also has a profound impact on the clock distribution network. Networks-on-chip (NoC) provides a regular communication fabric that helps to overcome these limitations. However, NoCs too will face bottlenecks in clocking beyond a few GHz… (More)
The gate oxide thickness in sub-70nm process technologies approaches the limit where direct gate tunneling current starts to play a significant role in both off-state and on-state transistors. In this paper, we present a novel reduced-gate SRAM (RG-SRAM) that uses two additional PMOS pass transistors to decrease the gate leakage dissipation in very deep… (More)
Due to the increasing process parameter variations and bitline capacitance, design of fast, reliable and robust read/write circuits for nanoscale SRAMs is a challenge. In this paper, we have investigated the effect of threshold voltage variations on the stability of read and write access schemes in SRAM designs. We considered three small signal read out and… (More)
In modern digital architectures, more and more emphasis has been laid on increasing the number of SRAMs in a SoC. However, with the increase in the number of SRAMs, the power requirement also increases, which is not desired. This calls for an urgent need for an SRAM with low dynamic and static power consumption and stability at the same time.