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We propose an algorithm for minimal-delay technology mapping for library-based designs. We show that subject graphs need not be decomposed into trees for delay minimization; they can be mapped directly as DAGs. Experimental results demonstrate that significant delay improvement is possible by this new approach.
In this paper we present a new app?'each to technology mapping foT aTea and delay for truth table based Field PTogI'ammabie Gate Arrays. We view the area and delay optimization duTing technology mapping as a case of clique partitioning foT which we have developed an eficient heuTistic. Additionally, we also ex-pioTe alternate decompositions using Shannon… (More)
In this paper we present a new approach to performance optimized mapping for Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs). Our approach is to first perform area efficient level reductions and then reinforce these by minimizing wirelengths using timing driven placement. Experimental results indicate that our approach produces designs that… (More)
In this paper we present a set cover based approach (SCP) to multi-way partitioning for minimum delay for Look-Up Table based FPGAs. SCP minimizes the number of chip-crossings on each circuit path with minimum logic duplication costs to achieve implementations with minimum delay and minimum number of chips. The overall complexity of SCP is (V 2).… (More)