Prashant Gurjar

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This paper is primarily deals the construction of high speed adder circuit using Hardware Description Language (HDL) in the platform Xilinx ISE 9.2i and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. The motivation behind this investigation is that an adder is a very basic building block of Arithmetic Logic Unit(More)
The 32-bit and 64-bit Floating point Arithmetic Logic Unit is a main part in the design of computers. The Aim of this paper is high performance through the pipelining concept compared to non-pipelining. This ALU includes all the arithmetic and logical operations. The Pipelined modules are independent of each other. The novelty is to design pipelined modules(More)
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