Pranjal Srivastava

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This paper investigates delay, power and area of several critical library components for high-performance, low-power microprocessor designs. To improve performance of a 0.18~pm technology at a supply voltage of 1.8 I(the proposed hybrid dual-V' (HDVT) circuit architectures enhance speed of high-v, by 21% while reducing leakage power dissipation of low-Vt by(More)
  • Suparshya Babu Sukhavasi, Susrutha Babu Sukhavasi, +21 authors John P Uyemura
  • 2012
In this paper a new approach of reducing power for a given system is developed that is self resetting logic, a parallel compressor is developed for multiplier by reducing its power with facilitation of this low power logic technique. By using this technique the power dissipation is significantly reduced with respect to other logics. By implementing the(More)
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