Pranav Balasubramanian

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Addition forms the basis of digital computer systems. A gate level self-timed full adder design, utilizing a pre-defined set of gates, available in a commercial synchronous standard cell library is discussed in this paper. The proposed adder satisfies Seitz’s weak-indication specifications and exhibits reduced data path delay in comparison with other(More)
A novel synthesis method for self-timed realization of arbitrary combinational logic functions is presented in this paper. The cost of self-timed implementation of a large number of conventional combinatorial benchmarks is provided. A new self-timed system configuration is also proposed in support of the synthesis heuristic that generally favors weakly(More)
In this paper, logical masking capability of commonly used logic gates such as NOT, AND/NAND, OR/NOR, and XOR/XNOR, when subject to single/multiple input faults, are analyzed from a mathematical perspective. A new metric, called Gate Error Metric (GEM) is proposed to study the extent of output error in these gates when subject to potential input fault(More)
GDI (gate diffusion input) based technique for low power combinational logic circuit design has been elaborately discussed and the advantage of this design style over static CMOS (SC) implementation and pass-transistor logic (PTL), with regard to power consumption, delay and area complexity is also described in recent literature (Morgenshtein, 2002). In(More)
A novel heterogeneously encoded dual-bit self-timed adder design is presented in this paper. Heterogeneous encoding refers to a combination of at least two different delay-insensitive encoding schemes, adopted for the inputs and outputs. The primary motivation being that higher order 1-of-n encoding protocols facilitate reduction in terms of the circuit(More)
We present a parallel implementation of three transmission switching algorithms. The first is based on a parallel search of all candidate lines, the second is based on a priority listing of lines and the third is based on decomposing the set of candidate lines in smaller subsets that are solved in parallel. We present a duality result that justifies the(More)
– A novel circuit topology for the CMOS based Incrementer/Decrementer circuit is presented in this paper. The design methodology is extensively based on Domino logic and it utilizes a simple two level look-ahead structure. The highly parallel, regular structure of the proposed 8-bit decision module (DM) macro cell makes this design, especially advantageous(More)
The problems associated with human error are very complicated with a number of dynamic factors influencing the outcome. Though it has been studied in detail in various industries with various tools and techniques, there is no comprehensive model available considering multiple factors that address the issue. In the field of Banking and Financial services,(More)
In this paper, we propose a logic synthesis technique that achieves delay optimization along with simultaneous depth reduction, apart from minimizing resources for a logic tree structure. Although it is a technology-independent scheme, it is guaranteed to enable better results overall, even after the technology-mapping phase, as evident from the results(More)
In this work, the authors consider the problem of logic minimization for a special class of Boolean networks, targeting low power implementation, using static CMOS logic. The authors start by framing a new binary minterm-value (BmV) matrix/binary max term-value (BMV) matrix for a binary 2-tuple, [mi (Mi), mj (Mj)], where HD (mi (Mi), mj (Mj)) is O(n), where(More)