Prakash Mohan Peranandam

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Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. The vital part missing in all these techniques is the so-called coverage of functionalities. This paper aims to tackle this problem by proposing a new method to verify the sequence(More)
— Current statistics attribute up to 75% of the overall design costs of digital hardware and embedded system development to the verification task. In recent years, the trend to augment functional with formal verification tries to alleviate this problem. Efficient property checking algorithms allow automatic verification of middle-sized designs nowadays.(More)
In this paper we describe an algorithm for distributed, BDD-based bounded property checking and its implementation in the verification tool SymC. The distributed algorithm verifies larger models and returns results faster than the sequential version. The core algorithm distributes partitions of the state set to computation nodes after reaching a threshold(More)
Symbolic property verification is an increasingly popular debugging method based on Binary Decision Diagrams (BDDs). The lack of optimization of the state space search is often responsible for the excessive growth of the BDDs. In this paper we present an accelerated symbolic property verification by means of a new <i>guiding</i> technique that automatically(More)
Dissertation der Fakultät f ¨ ur Informations-und Kognitionswissenschaften der Eberhard-Karls-Universität T ¨ ubingen zur Erlangung des Grades eines Doktors der Naturwissenschaften Acknowledgements Interdependence is a higher value than independence.-Stephen R. Covey. It is indeed hard to justice and acknowledge the help and contribution of all the people,(More)
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. In this paper we describe a new technique of property checking using symbolic simulation which can be applied to larger designs. This technique seamlessly integrate formal(More)
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