Pouya Asadi

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Multipliers are one of the most important building blocks in processors. This paper describes a low-power 32×32-bit parallel multiplier, designed and fabricated using a 0.13 μm double-metal doublepoly CMOS process. In order to achieve low-power operation, the multiplier was designed utilizing mainly pass-transistor logic circuits, without significantly(More)
  • Pouya Asadi
  • Journal of Circuits, Systems, and Computers
  • 2016
In this paper, a new multiplier using array architecture and a fast carry network tree is presented which uses dynamic CMOS technology. Di®erent reforms are performed in multiplier architecture. In the ̄rst step of multiplier operator, a novel radix-16 modi ̄ed Booth encoder is presented which reduces the number of partial products e±ciently. In this(More)
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