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WP2: Analysis of dressed human body characteristics 2 of 139 Credits This document was prepared by partners of the SAVE-U consortium. Please contact one of the following project partners for further information regarding this document or the project.
The crossbreeding between advanced microprocessor design and Field Programmable Gate Arrays (FPGAs) has produced the Field Programmable Processor Array, code named FPPA. The first integrated version has been targeted for low power consumption parallel processing. The FPPA is composed of a 10×10 array of RISC microcontrollers offering up to 500 MIPS at 5 MHz(More)
The power density inside high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating "hot spots" on the die. As a result, the performance, reliability and power consumption of the system degrade. To avoid these "hot spots", "temperature-aware" design has become a must. For(More)
Panagiotis Asimakopoulos: Optimizing the integration and energy efficiency of through silicon via-based 3D interconnects, PhD Thesis, The aggressive scaling of CMOS process technology has been driving the rapid growth of the semiconductor industry for more than three decades. In recent years, the performance gains enabled by CMOS scaling have been(More)
Notice of Copyright This material is protected under the copyright laws of the U.S. and other countries and any uses not in conformity with the copyright laws are prohibited. Copyright for this document is held by the creator — authors and sponsoring organizations — of the material, all rights reserved. Abstract— 3D stacking of dies is an enabler for(More)
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