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H.264/AVC is the latest video compression standard with highest coding efficiency, and the chip-area are increased significantly, especially the Integer-Motion-Estimation (IME) block. Thus the testability of H.264-IME is becoming more and more important. Currently, the scan-chain with Automatic Test Pattern Generation (ATPG) method is very popular for(More)
In this paper, we propose a novel test technique to achieve both acceptable number of test patterns (NTP) and hardware overhead (HO) by finding a balance between them. Novel bijective and scalable cells are proposed to apply the technique on ILA-based (Iterative-Logic-Array) architectures. A scalable cell consists of n bit-level cells and has both hardware(More)
In this paper, testable design techniques for variable block size motion estimators used in H. 264/AVC are proposed. The whole motion estimator can be viewed as an iterative logic array (ILA) consisting of basic cells (modules). Design-for-testability techniques are applied for the cell (module) function such that the M-testability conditions proposed in(More)
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