Po-Yang Hsu

Learn More
To alleviate high energy dissipation of cache memory, some research has proposed to reconfigure cache parameters such as cache capacity, number of way associative, and cache line size during program phase changes. However, none of previous research on cache reconfiguration takes <i>thread criticality</i> into consideration. In this paper, we dynamically(More)
Compressed cache was used in shared last level cache (LLC) to increase the effective capacity [1]. However, because of various data compression sizes, fragmentation problem of storage is inevitable in this cache design. When it happens, usually, a compaction process is invoked to make contiguous storage space. This compaction process induces extra cycle(More)
With the increasing non-recurring engineering cost of advanced process technologies , reconfigurable devices have received great attention in small and medium-volume integrated circuit designs. However, low logic diversity and slow timing performance limit the efficacy of field-programmable gate array (FPGA) and complex programmable logic device (CPLD). In(More)
In the routing architecture of a structured application-specific integrated circuit (ASIC), the crossbar is one of the most area-efficient switch blocks. Nevertheless, a dangling wire occurs when there is a routing bend in a crossbar switch. Dangling wires incur longer wire lengths as well as a higher interconnection capacitance. In this article, we tackle(More)
SUMMARY Most research projects with respect to energy saving are trying to improve power efficiency and are using software to manage the power systems in the power on mode; but in our design, we modify the original Suspend to RAM mode-S3 state, which is the 3 rd system state as defined by the ACPI specification, in order to reduce power consumption. We've(More)
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split off a long wire into several buffered wire segments for circuit performance improvement. In this paper, we are motivated to investigate the buffer insertion issues in LUT-based(More)
  • 1