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With no further shrinking of device size, 3-D chip stacking by through-silicon-via (TSV) has been identified as an effective way to achieve better performance in speed and power. However, such solution inevitably encounters challenges in thermal dissipation since stacked dies generate a significant amount of heat per unit volume. We leverage an integrated(More)
To alleviate high energy dissipation of cache memory, some research has proposed to reconfigure cache parameters such as cache capacity, number of way associative, and cache line size during program phase changes. However, none of previous research on cache reconfiguration takes <i>thread criticality</i> into consideration. In this paper, we dynamically(More)
In the routing architecture of a structured ASIC, crossbar is one of the most area efficient switch blocks. Nevertheless, dangling-wire occurs when there is a routing bend in crossbar switch. The dangling-wire incurs longer wire length as well as higher interconnection capacitance. In this paper, we are motivated to tackle dangling-wire routing issues for(More)
With the increasing NRE cost of advanced process technologies, reconfigurable devices receive great attention in small and medium volume IC designs. However, lower logic utilization and slower timing performance limit the efficacy of FPGA and CPLD. In this paper, we propose an efficient hybrid LUT/SOP reconfigurable design style to exploit both the(More)
In modern VLSI design, interconnection delay dominates the circuit delay due to its heavy downstream capacitance. Buffer insertion is a widely used technique for splitting a long wire into several buffered wire segments for circuit performance improvement. In this paper, we investigate buffer insertion issues in structured ASIC design style. We design the(More)
Compressed cache was used in shared last level cache (LLC) to increase the effective capacity [1]. However, because of various data compression sizes, fragmentation problem of storage is inevitable in this cache design. When it happens, usually, a compaction process is invoked to make contiguous storage space. This compaction process induces extra cycle(More)
Most of the research into saving energy which tries to improve the power efficiency and manage the power systems uses software control, but in our design we modify the S3 state to Deep S3 state in order to save power consumption by means of the Suspend to RAM mode. We redesign the circuit to save power in the PC standby mode. First, we recheck the whole(More)
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split off a long wire into several buffered wire segments for circuit performance improvement. In this paper, we are motivated to investigate the buffer insertion issues in LUT-based(More)
Changes in purine-related compounds of tilapia surimi product during processing were investigated. The washing step could, result in about 60% decrease of total purine content in tilapia mince during processing. The main released purine substance was inosine monophosphate. The major reducing effect was conducted in the first 10 min during washing. No(More)
With the increasing non-recurring engineering cost of advanced process technologies , reconfigurable devices have received great attention in small and medium-volume integrated circuit designs. However, low logic diversity and slow timing performance limit the efficacy of field-programmable gate array (FPGA) and complex programmable logic device (CPLD). In(More)