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—Ternary content addressable memory (TCAM) is extensively adopted in network systems. As routing tables become larger, energy consumption and leakage current become increasingly important issues in the design of TCAM in nano-scale technologies. This work presents a novel 65 nm energy efficient TCAM macro design for IPv6 applications. The proposed TCAM(More)
Voltage-dependent potassium channel Kv2.1 is widely expressed in mammalian neurons and was suggested responsible for mediating the delayed rectifier (I(K)) currents. Further investigation of the central role of this channel requires the development of specific pharmacology, for instance, the utilization of spider venom toxins. Most of these toxins belong to(More)
—The network-on-chip (NoC) architecture provides the integrated solution for system-on-chip (SoC) design. The buffer architecture and sizes, however, dominate the performance of NoC and influence on the design of arbiters in the switch fabrics. The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better(More)
In this paper, an adaptive congestion-aware routing algorithm is proposed for mesh network-on-chip (NoC) platforms. Depending on the traffic around the routed node, the proposed routing algorithm provides not only minimum paths but also non-minimum paths for routing packets. Both minimum and non-minimum paths are based on the odd-even turn model to avoid(More)
The clock storage elements using the low power technique are realized in this paper. The low swing conditional capture edge-trigged flip-flop(LSCCFF) suitable for the low switching activity applications is proposed. The single edge-trigger flip-flop uses the low swing voltage delay chain, the conditional capture technology and stacked technology to reduce(More)
Gain cell memories feature high speed, low power, and high density, which are suitable for SoC designs. In this paper, low power techniques to reduce leakage currents for 2T1D gain cell memory array are presented. For each memory cell, p-type gated diode storage device is applied. In addition, footer power gating and foot driver are applied on each memory(More)
—A 333MHz-1GHz all-digital multiphase delay-locked loop with precise multi-phase output has been designed with TSMC 130nm CMOS technology model. A modified binary search algorithm is proposed to match up a linear approximate delay element (LADE). The LADE property of linearity and insensitive to PVT variations is good for digitally-controlled delay element.(More)