Po-Tsang Huang

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—The network-on-chip (NoC) architecture provides the integrated solution for system-on-chip (SoC) design. The buffer architecture and sizes, however, dominate the performance of NoC and influence on the design of arbiters in the switch fabrics. The 2-level FIFO architecture is proposed. It simplifies the design of the arbitration algorithm and gets better(More)
—Ternary content addressable memory (TCAM) is extensively adopted in network systems. As routing tables become larger, energy consumption and leakage current become increasingly important issues in the design of TCAM in nano-scale technologies. This work presents a novel 65 nm energy efficient TCAM macro design for IPv6 applications. The proposed TCAM(More)
In this paper, an adaptive congestion-aware routing algorithm is proposed for mesh network-on-chip (NoC) platforms. Depending on the traffic around the routed node, the proposed routing algorithm provides not only minimum paths but also non-minimum paths for routing packets. Both minimum and non-minimum paths are based on the odd-even turn model to avoid(More)
This paper presents a novel self-equalized and skewless frequency-division multiplexing memory interface. To prove its feasibility, we have realized a 5-band QPSK transceiver in 40 nm CMOS to transmit up to 4 Gb/s through 10 orthogonal communication channels (each with 400 Mb/s) via on-chip TSV emulator with effective loading of 1 pF or 5-cm FR-4 PCB trace.(More)
Novel low power schemes for energy-efficient ternary content-addressable memory (TCAM) are presented in this paper. The butterfly match-line scheme is based on the pseudo-footless clock-data pre-charged architecture. It connects each pipelined stage in a butterfly style which significantly decreases both search time and power consumption. For applications(More)