Po-Kuan Huang

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With continuing shrinkage of technology feature sizes, the share of leakage in total energy consumption of digital systems continues to grow. Coordinated supply voltage and body bias throttling enables the compiler to better optimize the total energy consumption of the system in future technology nodes. We present a compilation technique that targets(More)
— We present a framework for development of streaming applications as concurrent software modules running on multi-processors system-on-chips (MPSoC). We propose an iterative design space exploration mechanism to customize MPSoC architecture for given applications. Central to the exploration engine is our system-level performance estimation methodology,(More)
We present a methodology for synthesizing streaming applications, modeled as task graphs, for pipelined execution on multi-core architectures. We develop a task graph extraction and characterization framework that accurately determines the structure, computation and communication characteristics of application task graph from its specification in C.(More)
With scaling of technology feature sizes, the share of leakage in total energy consumption of digital systems is on the rise. Conventional dynamic voltage scaling (DVS) techniques fail to accurately address the impact of scaling on system energy consumption breakdown, and hence, are incapable of achieving energy efficient solutions in all technology nodes.(More)
—Unlike their hard real-time counterparts, soft real-time applications are only expected to guarantee their " expected delay " over input data space. This paradigm shift calls for cus-tomized statistical design techniques to replace the conventional pessimistic worst case analysis methodologies. We present a novel statistical time-budgeting algorithm to(More)