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This paper presents a design of integrated analog-to-digital converter implemented in UMC CMOS 180nm technology dedicated to multichannel readout circuits. The successive approximation architecture with charge redistribution was proposed. A capacitive DAC is presented, where CMOS switches are described in detail in terms of speed and accuracy. In order to(More)
A 64-channel Neuro-Stimulation-Recording chip named NRS64 for neural activity measurements has been designed and tested. The NRS64 occupies 5×5 mm² of silicon area and consumes only 25 µW/channel. A low cut-off frequency can be tuned in the 60 mHz-100 Hz range while a high cut-off frequency can be set to 4.7 kHz or 12 kHz. A voltage gain can be set to 139(More)
Modern X-ray imaging applications require low noise and power, high rate readout front-end electronics. A widely used, dedicated for semiconductor detectors analog part of readout front-end architecture consists with charge sensitive amplifier and pulse shaping amplifier. To meet the requirements of pixel applications the simple architectures of front-end(More)
This paper presents a design of low-power charge redistribution ADC implemented in UMC 180nm CMOS. The described circuit is dedicated to a neurobiological experiment. A charge sharing capacitive DAC is discussed, with a resistive sub-DAC introduced as a way of increasing resolution with small area overhead. A 40 MHz synchronous latch with preamplifier is(More)
Multichannel integrated recording systems are the gate for our understanding of mammalian brain activity. For in vivo neurobiological brain experiment on animals moving free with the wireless control and data transmission it is necessary to eliminate the tethering effect and not to limit animals movement. We have designed in CMOS 180nm technology and sent(More)
This paper presents multi-objective optimization of a front-end electronics implemented in multichannel integrated circuit for silicon sensors readout in the Silicon Tracking System in the CBM experiment at the FAIR center. We present the optimization towards low-power (<; 8 mW/channel) and low-noise while keeping the channel pitch of 58 μm and(More)
Our report is on the simulation results and the design of the integrated circuit dedicated for inductive powering of a neural recording system on a chip. Four different voltage rectifiers were considered. designed to compare their power efficiency, drop out voltages, and ability to work in a megahertz range. Each of the full bridge rectifiers is equipped(More)
This paper presents a design of low power and low noise, high speed analog readout front-end electronic system implemented in CMOS 180 nm UMC technology for silicon strip detector. The front-end readout channel architecture consists of charge sensitive amplifier (CSA), pole-zero cancellation (PZC) circuit and complex pulse shaping amplifier (shaper). The(More)
We report on design of the 100 channel integrated circuit (10×10 pixel matrix) destined to complex neurobiology experiments. The chip is dedicated to both recording and stimulating neural activity and its predominant attributes comes from its individual digital control of both blocks and allocation of both in each of the pixel. Additionally, the(More)