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A fully-pipelined tile-able 1MB SRAM IP with a 0.127um<sup>2</sup> cell in a HKMG 28nm bulk technology has an area of 1.39mm<sup>2</sup>/MB with 79.2% array efficiency. It operates with 2-cycle latency up to 1GHz. The no-repair hardware has a circuit limited yield of 99.92 and 53% at 100 and 850MHz, respectively with 0.75V V<sub>DD</sub>. A Data Retention(More)
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