Pilin Junsangsri

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This paper presents a Ternary Content Addressable Memory (TCAM) cell that employs memristors as storage element. The TCAM cell requires two memristors in series to perform the traditional memory operations (read and write) as well as the search and matching operations for TCAM; this memory cell is analyzed with respect to different features (such as(More)
This paper presents a HSPICE macromodel of a phase change memory (PCM) cell. The model simulates not only the resistance change by phase (as corresponding to the two states, amorphous and crystalline), but also the temperature profile, the crystalline fraction during the programming and the drift behavior in resistance and threshold voltage. The proposed(More)
This paper presents a novel memory cell consisting of a memristor and ambipolar transistors. Macroscopic models are utilized to characterize the operations of this memory cell. A detailed treatment of the two basic memory operations (write and read) with respect to memristor features is provided; particular, emphasis is devoted to the threshold(More)
This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for SEU tolerance. The proposed NVSRAM cell consists of a 6T SRAM core and a Resistive RAM (RRAM), made of a 1T and a Programmable Metallization Cell (PMC). The proposed cell has concurrent error detection (CED) and correction capabilities; CED is accomplished using a dual-rail(More)
This paper presents the novel design of a Ternary Content Addressable Memory (TCAM); different from existing designs found in the technical literature, this cell utilizes a single Phase Change Memory (PCM) as storage element and ambipolarity for comparison. A memory core consisting of a CMOS transistor and a PCM is employed (1T1P); for the search operation,(More)
This paper deals with a so-called racetrack memory (also commonly known as a domain-wall memory). Novel circuits for implementing the write, the read, and the shift operations of a Perpendicular Magnetic Anisotropic (PMA) based racetrack cell are initially introduced; the proposed circuits are very efficient in terms of numerous figures of merit, such as(More)
This paper presents the design of a Content Addressable Memory (CAM) cell. This cell utilizes a Phase Change Memory (PCM) as storage element and an ambipolar transistor for data comparison; the operation of the ambipolar transistor is controlled by voltage at the polarity gate. A memory core consisting of a CMOS transistor and a PCM is employed (1T1P). For(More)
This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6T SRAM core, a Resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error(More)