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This paper presents a HSPICE macromodel of a phase change memory (PCM) cell. The model simulates not only the resistance change by phase (as corresponding to the two states, amorphous and crystalline), but also the temperature profile, the crystalline fraction during the programming and the drift behavior in resistance and threshold voltage. The proposed(More)
This paper presents a Ternary Content Addressable Memory (TCAM) cell that employs memristors as storage element. The TCAM cell requires two memristors in series to perform the traditional memory operations (read and write) as well as the search and matching operations for TCAM; this memory cell is analyzed with respect to different features (such as(More)
This paper presents a new HSPICE macromodel of a Programmable Metalization Cell (PMC). The electrical characteristics of a PMC are simulated by using a geometric model that considers the vertical and lateral growth/disolution of the metallic filament. The selection of the parameters is based on operational features, so the electrical characterization of the(More)
This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for SEU tolerance. The proposed NVSRAM cell consists of a 6T SRAM core and a Resistive RAM (RRAM), made of a 1T and a Programmable Metallization Cell (PMC). The proposed cell has concurrent error detection (CED) and correction capabilities; CED is accomplished using a dual-rail(More)
This paper presents a novel memory cell consisting of a memristor and ambipolar transistors. Macroscopic models are utilized to characterize the operations of this memory cell. A detailed treatment of the two basic memory operations (write and read) with respect to memristor features is provided; particular, emphasis is devoted to the threshold(More)
—This paper presents a system-level scheme to alleviate the effect of resistance drift in a multilevel phase change memory (PCM) for data integrity. In this paper, novel criteria of separation of the PCM resistance for multilevel cell storage and selection of the threshold resistances between levels are proposed by using a median based method based on a row(More)
This paper proposes a low-power non-volatile programmable inverter cell (NVPINV) that can be used with a COGRE (i.e. a compactly organized generic reconfigurable element) circuit to store the correct information for programming when establishing the desired logic function. The programmable data in the cell is read from a non-volatile SRAM (NVSRAM); two RMs(More)