Piet Engelke

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We present a technique for making a circuit ready for logic built-in self test by masking unknown values at its outputs. In order to keep the silicon area cost low, some known bits in output responses are also allowed to be masked. These bits are selected based on a stuck-at -detection based metric, such that the impact of masking on the defect coverage is(More)
The authors present a simulator for resistive-bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look up, thus, exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; interaction of fault effects in current time frame and earlier time frames is elaborated(More)
Defects not described by conventional fault models are a challenge for state-of-the-art fault diagnosis techniques. The X-fault model has been introduced recently as a modeling technique for complex defect mechanisms. We analyze the performance of the X-fault diagnosis for a number of defect classes leading to highly complex circuit behavior on electrical(More)
Test application at reduced power supply voltage (or VLV testing) is a cost-effective way to increase the defect coverage of a test set. Resistive short defects are a major contributor to this coverage increase. Using a probabilistic model of these defects, we quantify the coverage impact of VLV testing for different voltages. When considering the coverage(More)
We present a simulator which determines the coverage of small-delay faults, i.e., delay faults with a size below one clock cycle, caused by resistive-open defects. These defects are likely to escape detection by stuck-at or transition fault patterns. For the first time, we couple the calculation of the critical size of a small-delay fault with the(More)
We present a fully automated flow to generate test patterns for interconnect open defects. Both inter-layer opens (openvia defects) and arbitrary intra-layer opens can be targeted. An aggressor-victim model used in industry is employed to describe the electrical behavior of the open defect. The flow is implemented using standard commercial tools for(More)
We study the behavior of feedback bridging faults with nonzero bridge resistance. We demonstrate that a test vector may detect the fault, not detect the fault or lead to oscillation, depending on bridge resistance. Even loops going through a gate with controlling values on its side inputs (which we call disabled loops) expose non-trivial behavior. We(More)