Pierre Souillot

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This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-Fat-Tree topology, and an upward network using hierarchy. Studies based on the Rent's Rule show that wiring and switch requirements in the MFPGA grow slower than in(More)
Creation of large FPGAs needs radical efficient changes in architecture to improve speed, density and software mapping time. Based on industry experience with standard ASICs, we believe that partitioning and hierarchy become an obligation for FPGA hardware and software developments. As an alternative we propose a new Multilevel hierarchical FPGA (MFPGA)(More)
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