Pierre Leray

Learn More
We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (Network on Chip) structure inside a FPGA. In the context of a SDR (Software Defined Radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The(More)
— This paper presents the ANR project IDROMel, which aims at developing reconfigurable SDR (Software Defined Radio) and Cognitive Radio (CR) equipments. IDROMel is a 3 years project that started in 2005 and finishes in 2009. The main objective of IDROMel is to define, develop and validate a powerful SDR and CR platform combining very last technology(More)
This paper is about the implementation of a MIMO V-BLAST (Vertical Bell Laboratories Layered Space-Time) square root decoder in a FPGA using dynamic partial re-configuration. The decoder architecture is based on four CORDIC (COordinate Rotation DIgital Computer) Units. Among these CORDIC units, three are used in rotation mode and the fourth one is used in(More)
  • 1