Pier Luigi Rolandi

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This paper describes a digital signal processor based on a multi-context, dynamically reconfigurable datapath, suitable for inclusion as an IP-block in complex SoC design projects. The IP was realized in CMOS 090 nm technology. The most relevant features offered by the proposed architecture with respect to state of the art are zero over head for switching(More)
An AC-coupled 3D memory interface for chip-to-chip communication is implemented in 90nm CMOS technology. It transfers 128 bit words between stacked SRAMs in an ARM-based System on Chip (SoC) platform at 250MHz. This interface requires 0.05mm<sup>2</sup> of occupation area and achieves a 32Gbit/sec of throughput and an average energy consumption of(More)
A 1GOPS dynamically reconfigurable processing unit with embedded Flash memory and SRAM-based FPGA targets image-voice processing and recognition applications. Code, data and FPGA bitstreams are stored in the embedded Flash memory and are independently accessible through 3 content-specific, 64-bit I/O ports with a peak read rate of 1.2GB/s. The system is(More)
Capacitive interconnections are very promising structures for high-speed and low-power signaling in 3D packages. Since the performance of AC links, in terms of Band-Width and Bit-Error-Rate (BER), depends on assembly and synchronization accuracy we performed a statistical analysis of assembly procedures and communication circuits. In this paper we present a(More)
Signal propagation delay and leakage power dissipation of FPGAs mainly depend on the routing architecture. In this paper we propose solutions; adopted in an embedded FPGA developed both in 90nm and 65nm STM technology, which minimize the subthreshold current of the switch and connection blocks. Our approach leads to a reduction of more than one order of(More)
Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog implementation. The architectures which result can be ultra efficient both in terms of high density and low power consumption. We have implemented a small (16x512) analog(More)
This standard flash-EEPROM contains 1M cells with multi-level programming of up to 64 digital levels per cell, providing a prototype of a 6Mb memory with 257Mb/cm 2 array density. High-density digital storage techniques for floating gate devices (>8 levels) require the use of feedback in the programming loop (pulse and verify method) and substantially(More)