Phiroze N. Parakh

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Over the last five years the VLSI Placement community achieved great strides in the understanding of placement problems, developed new high-performance algorithms, and achieved impressive empirical results. These advances have been supported by non-trivial benchmarking infrastructure, and future achievements are set to draw on benchmarking as well. In this(More)
The development of a PowerPC™ fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementation. Manufactured in Motorola's 0.5—µm Complementary Gallium Arsenide process, the device operates(More)
In this paper, we describe an accurate metric (perimeter-degree) for measuring interconnection complexity and effective use of it for controlling congestion in a multilevel framework. Perimeter-degree is useful for uniformly spreading interconnection density. In modern designs interconnects consume significant area and power. By making interconnect spread(More)
Researchers at the University of Michigan, in collaboration with their partners from Motorola and Cascade Design Automation, are developing design methodologies and automated tools for use in implementing high clock rate digital “systems-on-anMCM.” The PUMA processor, a demonstration vehicle that executes a subset of the PowerPC instruction set, will be(More)
A self-aligned complementary GaAs (CGaAsTM) technology developed at Motorola for low-power, portable, digital and mixed-mode circuits is being extended to address highspeed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature,(More)
The congestion minimization techniques have become more important due to the shrinking geometries and “taller” interconnects, causing numerous design convergence problems. Also, multilevel placement algorithms are becoming more prevalant due to their ability to natively incorporate mixed-mode placement, in addition to their ability to scale to very large(More)
A Lithography Friendly Design solution entails the creation of a single physical layout which satisfies design constraints while concurrently accounting for process and manufacturing variations. At 45nm and below, above and beyond exponential growth in complexity (and mask-size), Optical Proximity Correction fails to render certain layout topologies. Thus a(More)
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