Phillip Jozwiak

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A silicon‐proven multi‐finger turn‐on (MFT) design technique that enables ESD width scaling combined with very low dynamic on‐resistance is presented in various implementations. It can be applied to (self‐ protecting) drivers and/or ESD protection design. Using a novel merged ballast circuit design, very compact ESD protection configurations with an ESD(More)
EOS/ESD symposium 2002 This paper presents a novel SCR for power line and local I/O ESD protection. The HHI‐SCR exhibits a dual ESD clamp characteristic: low‐ current high‐voltage clamping and high‐current low‐voltage clamping. These operation modes enable latch‐up immune normal operation as well as superior full chip ESD protection. The minimum latch(More)
EOS/ESD symposium 2001 In this paper, design aspects, operation, protection capability and applications of SCRs in deep submicron CMOS are addressed. A novel Grounded‐Gate Nmos Triggered SCR device (GGSCR) is introduced and compared to the LVTSCR. Experimental verification, including endurance testing, demonstrates that GGSCRs can fulfill all ESD protection(More)
This paper presents a protection strategy for ultra‐sensitive IO's containing thin gate oxides, while combining two complementary ESD design approaches: 1. Low‐voltage diode‐chain triggered SCR clamps that allow for efficient voltage clamping. 2. Active‐Source‐Pump circuits applied for effective expansion of narrow ESD design windows for ultra‐thin GOX(More)
This paper presents three novel design techniques, which combined fulfill all major requirements posed on large driver and Electro Static Discharge (ESD) protection transistors: minimum area consumption, good ESD robustness and optimized normal operation. Transistors protecting 5V/um2 Human Body Model (HBM) were demonstrated. Significant silicon area(More)
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