Phillip Christie

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This special session adresses the problems that designers face when implementing analogand digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages,(More)
Functional yield is a term used to describe the percentage of dies on a wafer that fail due to catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires, and cuts, which result in broken wires. The probability of failure is therefore determined by(More)
This work examines the impact of interstratal interconnect density on the wire-length distribution and on the performance of three-dimensional integrated circuits. A model for the wire-length distribution of 3D-ICs, which takes into account the interstratal interconnect density, is proposed first. The wire-length distributions of 2D-IC, homogeneous (ideal),(More)
Cycle time models perform an <i>a-priori</i> calculation of local signal delays by estimating the lengths of wires connecting different levels of synchronously clocked logic elements. Typically, a signal will have to pass through approximately 15-25 layers of logic during a single clock cycle and it is has been assumed that this number is sufficiently large(More)
The variation of in-plane interconnect geometry (pitch and width) as a function of wiring level results in improved system level performance because the properties of each wiring layer may be tailored to the characteristic lengths of the wires allocated to it. Performance metrics such as interconnect functional yield, and power dissipation are well suited(More)
Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexity and boosting the performance density. First, we analyze characteristics of the Task-Level Parallelism in(More)
The re-use of functional blocks within a large system on a chip (SoC) design results in a design trade-off between local intra-block and global inter-block communication. This paper develops a mathematical model to analyze the wire length distributions resulting from two possible layout strategies: the optimization of block terminal locations to minimizing(More)