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Journals and Conferences
A method of direct input reference feed-forward compensation is proposed and discussed for all digital phase locked loop based synthesizers. The practical issues in implementing the system are addressed, and analysis of the feed-forward estimation error on the system is performed. A sample model was created and simulated. Simulation shows the effect of the… (More)
The All-Digital Phase-Locked Loop has several advantages when compared with traditional charge-pump based PLL. We will introduce some of its advantages in this paper, showing how they can be used to improve the system’s performance. In addition, performance limitations of the system will be discussed.
Conventional clock and data recovery (CDR) using a phase locked loop (PLL) suffers from problems such as long lock time, low frequency acquisition and harmonic locking. Consequently, a CDR system using a time to digital converter (TDC) is proposed. The CDR consists of simple arithmetic calculation and a TDC, allowing a fully digital realization. In… (More)