Philippe Manet

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Despite recent management guidelines, no recent study has evaluated outcomes in ICU patients with status epilepticus (SE). An 8-year retrospective study. Observational study in 140 ICU patients with SE, including 81 (58%) with continuous SE and 59 (42%) with intermittent SE (repeated seizures without interictal recovery). The 95 men and 45 women had a(More)
1Université catholique de Louvain, Place du Levant 3, 1348 Louvain-la-Neuve, Belgium 2Thales Communications, Boulevard de Valmy 160, 92704 Colombes, France 3CESVIT MICROELETTRONICA, Via F. Frediani, 59100 Prato, Italy 4MBDA, Avenue Réaumur 1, 92358 Le Plessis Robinson, France 5Tecnopolis CSATA, Str P. Casamassima km 3, 70010 Valenzano Bari, Italy 6Aerospace(More)
Embedded systems allow application-specific optimizations to improve the power/performance trade-off. In this paper, we show how application-specific hashing of the address can eliminate a large number of conflict misses in caches. We consider XOR-functions: each set index bit is computed as the XOR of a subset of the address bits. Previous work has(More)
With the increasing capacity of FPGAs following the Moore's law, it is possible to build in a single FPGA, a large system on chip (SoC) composed by several cores. Their performances depend strongly on their interconnection structure. Traditional and hierarchical busses are not suitable to be used. The Networks on Chip (NoC), due to their characteristics(More)
As the trend in reconfigurable electronics goes towards strong integration, FPGA devices are becoming more and more interesting. They are already used for safety-critical applications such as avionics [9]. Latest FPGA's also enable new techniques such as dynamic partial reconfiguration (DPR), allowing new possibilities in terms of performance and(More)
Out-of-order execution significantly increases the performanceof superscalar processors. The out-of-order execution mechanismis, however, energy-inefficient, which inhibits scaling superscalar processorsto high issue widths and large instruction windows. In this paper, we build on the observation that between 19% and 36% of the instructions are immediately(More)
This paper presents the RECOPS project that aims to study the use of reconfiguration in military applications. The project explores the new potentials and possibilities offered by reconfigurable components like FPGA. It identifies specificities related to the use of this technology in military applications and proposes solutions to support them. Specific(More)
In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural level, by using extensive clock and data gating, and by completely redesigning the micro-architecture. We also present original clock gating techniques: pre-computed clock gating. To validate these techniques,(More)
This paper presents the RECOPS project that aims to study the use of reconfiguration in military applications. The project explores the new potentials and possibilities offered by reconfigurable components like FPGA. It identifies specificities related to the use of this technology in military applications and proposes solutions to support them. Specific(More)
The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementations.(More)