Philippe Lorenzini

Learn More
1383-7621/$ see front matter 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.sysarc.2013.06.007 q This document is a collaborative effort. ⇑ Corresponding author. Tel.: +33 1 78 85 65 48. E-mail addresses: Francois.Duhem@unice.fr (F. Duhem), Fabrice.Muller@unice.fr (F. Muller), willy.aubry@labri.fr (W. Aubry),(More)
As a matter of fact, there is a lack of tools handling partially reconfigurable FPGAs modeling at a high level of abstraction that give sufficient degree of freedom to the designer for testing scheduling algorithms. In this paper, we present our methodology to fill this gap and take into account partial reconfiguration into high-level modeling with SystemC.(More)
  • 1