Philippe Hurat

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As the semiconductor industry enters the subwavelength era where silicon features are much smaller that the wavelength of the light used to create them, a number of “subwavelength” technologies such as Optical Proximity Correction (OPC) and Phase-Shifting Masks (PSM) have been introduced to produce integrated circuits (ICs) with acceptable(More)
Until the move to the 130nm node, yield was an issue only for product engineers and engineers on the production line. Design engineers did not need to think explicitly about yield, or understand the manufacturing process. Beginning at the 130nm node, yield has become more problematic, and the defect mechanisms that contribute to yield loss are very(More)
Lithography, etch and stress are dominant effects impacting the functionality and performance of designs at 65nm and below. This paper discusses pattern dependent variability caused by these effects and discusses a model-based approach to extracting this variability. A methodology to gauge the extent of this pattern dependent variability for standard cells(More)
To implement high-performance IC designs, a great deal of development effort goes toward providing optimization capabilities for popular cell-based methodologies. Cell-based methodologies rely on the availability of standard-cell libraries and design tools such as synthesis, verification and place-and-route tools. Although the industry is focusing mainly on(More)
At 65 nm, device and interconnect features are well below the wavelength of light used to pattern them, and shape variations significantly impact circuit characteristics. A simulation methodology to predict changes in circuit characteristics due to systematic lithography and etch effects is described and validated in silicon. A device model, which captures(More)
A current density-based model that incorporates narrow width effects is proposed to predict the drawn current of transistors that exhibit non-uniform device geometry. A continuous, integrable, analytical model of current density that includes the details of stress, edge effects and dopant loss/pileup is first calibrated to silicon data or existing SPICE(More)