Sigma-delta modulation, associated with oversampling and noise shaping, is a well-known technique used in high-accuracy A/D converters. Such converters, required in telecommunications applications, are characterized by ac performance such as signal-to-noise ratio. Moreover , they are mainly dedicated to applications which can tolerate offset and gain… (More)
Index Terms—Analog-to-digital conversion, CMOS analog integrated circuits, delta-sigma modulation, incremental data converters , low-power electronics, mixed analog-digital integrated circuits , oversampling A/D converters, switched-capacitor circuits.
In this paper the theoretical operation of incremental (charge-balancing) delta-sigma (DeltaSigma) converters is reviewed, and the implementation of a 22-bit incremental A/D converter is described. Two different analyses of the first-order incremental converter are presented, and based on these results two extensions to higher-order modulators are proposed.… (More)
The CARIOCA front-end is an amplifier discriminator chip, using 0.25Pm CMOS technology, developed with a very fast and low noise preamplifier. This prototype was designed to have input impedance below 10:. Measurements showed a peaking time of 14ns and noise of 450e-at zero input capacitance, with a noise slope of 37.4 e-/pF. The sensitivity of 8mV/fC… (More)
A very fast and low noise front-end implemented in 0.25µm CMOS process is reported. The CARIOCA amplifier discriminator chip has input impedance of 10Ω, to be compatible with sensors of large capacitance, and a peaking time of 14ns. The sensitivity of 8mV/fC remains almost unchanged up to a sensor capacitance of 120pF. A noise figure of 450e-(0.07fC rms) at… (More)