Philippe Coussy

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THE GROWING CAPABILITIES of silicon technology and the increasing complexity of applications in recent decades have forced design methodologies and tools to move to higher abstraction levels. Raising the abstraction levels and accelerating automation of both the synthesis and the verification processes have for this reason always been key factors in the(More)
This paper addresses the design of multimode architectures for digital signal and image processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named GAUT. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single register transfer level(More)
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named <b>GAUT.</b> Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single <b>RTL</b> hardware(More)
To meet the higher data rate requirement of current and future communication standards, numerous techniques to decode Turbo and LDPC codes on hardware architecture are developed. Unfortunately, interleaving laws that are used in these codes often result in memory access conflicts when massively parallel architectures are targeted which considerably limits(More)
Neuromorphic engineering is a fast growing field with great potential in both understanding the function of the brain, and constructing practical artifacts that build upon this understanding. For these novel chips and hardware to be useful, hardware compatible applications and simulation tools are needed. We argue that the neural circuit approach, in which(More)
GAUT is an open source High-Level Synthesis tool. From a bitaccurate C/C++ specification it automatically generates a RTL architecture described in VHDL that can be used by commercial logical synthesis tools like ISE (Xilinx), Quartus (Altera). GAUT also generates TLM and CABA SystemC simulation models for the SocLib virtual prototyping platform.
DESIGN COMPLEXITY is continually rising with the higher levels of integration implied by Moore’s law. Functional complexity increases with our ability to incorporate more computation in SoCs and to create more complex applications. Additional complexity is also introduced in the design process by the need to control power consumption and to tackle(More)
Coarse-Grained Reconfigurable Architectures (CGRAs) are promising high-performance and power-efficient platforms. However, their uses are still limited by the capability of mapping tools. This abstract paper outlines a new automated design flow to map applications on CGRAs. The interest of our method is shown through comparison with state of the art(More)
For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low(More)
For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low(More)