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This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, offset and slim spacers, advanced co-implants, Nisi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the(More)
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676µm 2 and 0.54µm 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology(More)
Routing holes in wireless sensor networks (WSN) do occur due to several reasons, including cases caused by natural obstacles or disaster suffered areas. Computing the exact boundary of a hole is possible [5], but can be impractical with large holes. In this paper, we consider the problem of how to approximate a hole by a simplistic shape, covering polygon(More)
Holes in sensor network are regions without operating nodes which may occur due to several reasons, including cases caused by natural obstacles or disaster suffered areas. Determining the location and shape of holes can help to monitor these disaster events (such as volcano, tsunami, etc.) or help to make smart, early routing decisions for circumventing a(More)
A critical issue in designing efficient routing algorithms for wireless sensor networks (WSN) is dealing with holes which do occur due to several reasons, including cases caused by natural obstacles or disaster suffered areas. Traditional solutions utilize perimeter routing techniques that however lead to traffic concentration on the nodes on the hole(More)
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