Petra Nordholz

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During back-end verification of digital circuits, analog circuit simulation is an indispensable, but time consuming, process. To reduce simulation time, current source models (CSMs) have been proposed to replace transistor netlists of logic cells. In this paper, physically motivated requirements for accurate CSMs are derived. By employing the topological(More)
A fast characterization method for current source models (CSM) is proposed. It analyses the given transistor netlist of CMOS logic cells to determine both static and dynamic CSM parameters in the same DC simulation. To account for the influence of parasitic elements in large logic cells, an additional low pass filter is inserted to the CSMs. AC analysis is(More)
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