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We present a two-level Boolean minimization tool (BOOM) based on a new implicant generation paradigm. In contrast to all previous minimization methods, where the implicants are generated bottom-up, the proposed method uses a top-down approach. Thus instead of increasing the dimensionality of implicants by omitting literals from their terms, the dimension of(More)
We propose a new built-in self-test (BIST) method based on a combination of a pseudo-random test method with a deterministic test. This enables us to reach a high fault coverage in a short test time and with a low area overhead. The main feature of the method is that there are no memory elements to store the deterministic test patterns; the test patterns(More)
  • Petr Fiser
  • 2007
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design method. The pattern generator should be as small as possible, whereas patterns generated by it should guarantee satisfactory fault coverage. Weighted random pattern generators offer(More)
Testing of digital circuits seems to be a completely mastered part of the design flow, but constrained test patterns generation is still a highly evolving branch of digital circuit testing. Our previous research on constrained test pattern generation proved that we can benefit from an implicit representation of test patterns set in CNF (Conjunctive Normal(More)
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease(More)
In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method is targeted to systems on chip (SoCs)provided with the P1500 test standard. The RESPIN architecture can be used for test patterns decompression. The main idea is based on finding the(More)
In a pseudo-random testing of combinational circuits the pattern generator produces test vectors that are being applied to the tested circuit. The nature of the generator thus directly influences the fault coverage achieved. In this paper we discuss an influence of the type of the pseudo-random pattern generator on the fault coverage. In most cases the LFSR(More)