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- George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
- IEEE Trans. on CAD of Integrated Circuits and…
- 2003

This paper presents an approach to the wordlength allocation and optimization problem for linear digital signal processing systems implemented as custom parallel processing units. Two techniques are proposed, one which guarantees an optimum set of wordlengths for each internal variable, and one which is a heuristic approach. Both techniques allow the user… (More)

- Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
- Design Autom. for Emb. Sys.
- 2002

This paper compares three heuristic search algorithms: genetic algorithm (GA), simulated annealing (SA) and tabu search (TS), for hardware-software partitioning. The algorithms operate on functional blocks for designs represented as directed acyclic graphs, with the objective of minimising processing time under various hardware area constraints. The… (More)

- N. Pete Sedcole, Peter Y. K. Cheung
- FPT
- 2006

Semiconductor scaling causes increasing and unavoidable within-die parametric variability. This paper describes accurate measurement techniques for characterising both systematic and stochastic delay variability in FPGAs. Results and analysis are presented from measurements made on a sample of 90nm devices, showing that delay per logic element varies… (More)

- Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
- 12th Annual IEEE Symposium on Field-Programmable…
- 2004

This paper presents a method that offers a uniform treatment for bit-width optimisation of both fixed-point and floating-point designs. Our work utilises automatic differentiation to compute the sensitivities of outputs to the bit-width of the various operands in the design. This sensitivity analysis enables us to explore and compare fixed-point and… (More)

Automatic bitwidth analysis is a key ingredient for highlevel programming of FPGAs and high-level synthesis of VLSI circuits. The objective is to find the minimal number of bits to represent a value in order to minimize the circuit area and to improve efficiency of the respective arithmetic operations, while satisfying user-defined numerical constraints. We… (More)

This paper presents a method for evaluating functions in hardware based on polynomial approximation with non-uniform segments. The novel use of nonuniform segments enables us to approximate non-linear regions of a function particularly well. The appropriate segment address for a given function can be rapidly calculated in run time by a simple combinational… (More)

This paper presents a method for evaluating functions based on piecewise polynomial approximation with a novel hierarchical segmentation scheme. The use of a novel hierarchy scheme of uniform segments and segments with size varying by powers of two enables us to approximate nonlinear regions of a function particularly well. This partitioning is automated:… (More)

- Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung
- IEEE Trans. VLSI Syst.
- 2005

This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2 ), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple -bit serial multipliers; by changing the number of such serial… (More)

- Sutjipto Arifin, Peter Y. K. Cheung
- ACM Multimedia
- 2007

Extracting video structures is important for video indexing and navigation in large digital video archives. It is usually achieved by video segmentation algorithms. Little research efforts has been invested on segmentation solutions that utilize the video's emotional content. These solutions not only have the potential of providing better performances than… (More)

- Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung
- FCCM
- 1997

This paper describes a framework and tools for automating the production of designs which can be partially recon gured at run time. The tools include: (i) a partial evaluator, which produces con guration les for a given design, where the number of con gurations can be minimised by a process known as compile-time sequencing; (ii) an incremental con guration… (More)