Peter Trajmar

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In this paper, we present a graph based technology mapping algorithm, called DAG-Map, for delay optimization in lookup-table based FPGA designs. Our algorithm carries out technology mapping and delay optimization on the entire Boolean network, instead of decomposing the network into fanout-free trees and mapping each tree separately as in most previous FPGA(More)
We present a graph based technology mapping algorithm , called DAG-Map, for delay optimization in lookup-table based FPGA designs. Our algorithm carries out technology mapping and delay optimization on the entire Boolean network, instead of decomposing it into fanout-free trees and mapping each tree separately as in most previous algorithms. As a(More)
We present a graph based technology mapping algorithm , called DAG-Map, for delay optimization in lookup-table based FPGA designs. Our algorithm carries out technology mapping and delay optimization on the entire Boolean network, instead of decomposing it into fanout-free trees and mapping each tree separately as in most previous algorithms. As a(More)
He has served on the program committees of a number of VLSI CAD conferences, and chaired the 4th ACM/SIGDA Physical Design Workshop. His research interests include computer-aided design of VLSI circuits, rapid system prototyping, and design and analysis of combinatorial and geometric algorithms. where he is pursuing his Ph.D. degree. His research interests(More)
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