Peter Stolk

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A new mechanism causing deterioration of the threshold voltage matching performance of MOSFETs is described. We demonstrate that this effect depends on several fundamental CMOS device architecture aspects such as the source/drain implant energies, the gate layer thickness, a gate top oxide layer thickness and the poly-silicon gate morphology. It is(More)
We have developed in this work a new characterization methodology which includes stressing and measurement in a single experimental step. This overcomes the influence of the hole detrapping effect in ultra-thin gate-oxides (T/sub OX/=1.4-1.6 nm) and enables comparison of gate-oxide nitridation impacts on negative bias temperature instability (NBTI). This(More)
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