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Recent trends in the commercial use of fractional-N frequency synthesis can be attributed to the characteristic of independent loop bandwidth-channel spacing that results in low phase noise and relaxes the Phase-Locked Loop (PLL) design constraints. This paper reviews several techniques used to implement fractional-N frequency synthesizers and discusses the(More)
Intravascular Ultrasound (IVUS) is a predominant imaging modality in interventional cardiology. It provides real-time cross-sectional images of arteries and assists clinicians to infer about atherosclerotic plaques composition. These plaques are heterogeneous in nature and constitute fibrous tissue, lipid deposits and calcifications. Each of these tissues(More)
In this paper, we introduce a framework for simulating intravascular ultrasound (IVUS) images and radiofrequency (RF) signals from histology image counterparts. We modeled the wave propagation through the Westervelt equation, which is solved explicitly with a finite differences scheme in polar coordinates by taking into account attenuation and non-linear(More)
Coronary artery disease leads to failure of coronary circulation secondary to accumulation of atherosclerotic plaques. In adjunction to primary imaging of such vascular plaques using coronary angiography or alternatively magnetic resonance imaging, intravascular ultrasound (IVUS) is used predominantly for diagnosis and reporting of their vulnerability. In(More)
The current mode digital-to-analog converter (iDAC) has been widely used in finite-impulse response (FIR) filter implementations as it is well-suited for high­ speed operation. This paper proposes a novel solution to reduce the signal feed-through problem commonly encountered in current mode digital-to-analog converters in pre-emphasis circuits. To improve(More)
Decision feedback equalization (DFE) is a popular technique to counteract inter-symbol interference (ISI) in high-speed backplane data communications. Quarter-rate clock timing for DFE circuit design is proposed to alleviate the speed requirement of the clock timing. A receiver implemented in 0.18-µm CMOS technology demonstrates 6.25Gb/s and 8Gb/s operation(More)
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