Peter Gutberlet

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A main step in the high level synthesis is the data path synthesis consisting of allocation, scheduling and assignment. This paper presents an allocation algorithm designed for an environment where the allocation precedes scheduling and assignment. This algorithm selects the hardware components in type and number fully automatically and supports a realistic(More)
As VHDL spreads widely, its usage for abstract modeling and synthesis is limited by the simulation semantics, which necessitates the specification of the interface signal transitions at bit level with exact timing. This paper shows a methodology to model the interface of a behavioural description suited for high level synthesis where different abstraction(More)
It is the goal of the recently developed and herewith presented scheduling algorithm to optimize the timing behaviour within automated circuit synthesis. The algorithm is a part of the CADDY-Synthesis-System (CAddy SCHeduling). Basis is a list scheduling algorithm which is controlled by a heuristic rating function. The allocated resources can be modelled in(More)
AS VHDL spreads widely, its usage for abstract modeling and synthesis is limited by the simulation semantics, which necessitates the speciftcation of the interface signal transitions at bit level with exact timing. This paper shows a methodology to model the integace of a behavioural description suited for high level synthesis where different abstraction(More)
PARAGON provides a platform for hardware-software partitioning for systems specified in the C++ language. In this paper†, we are going to introduce PARAGON emphasizing how the synchronization and communication among the used processors are built during and after the partitioning. The partitioned specification consists of multiprocessors communicating with(More)