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An interesting technique for doing FIFO design is to perform asynchronous comparisons between the FIFO write and read pointers that are generated in clock domains that are asynchronous to each other. The asynchronous FIFO pointer comparison technique uses fewer synchronization flip-flops to build the FIFO. The asynchronous FIFO comparison method requires(More)
SRAM-based high-density FPGAs offer many advantages in satellite and other aerospace applications. A perceived drawback is the susceptibility of configuration latches to radiation-induced upsets. Heavy-ion testing at Brookhaven have established that the specially processed Xilinx XQR4000XL-family devices exhibited latch-up immunity at LET>100 MeVcm 2 /mg at(More)
Field-programmable logic started out as glue logic between Òreal ICs.Ó Over the past decade, however, progress in IC technology has made it possible to implement ÒrealÓ functions in FPGAs. Now, bigger and faster FPGAs are becoming system platforms that combine several ÒrealÓ systems functions on a single chip. even microprocessors and memories. ÒBiggerÓ(More)
All Virtex® and Spartan® FPGAs include many block RAMs. Even the smallest Virtex device has dozens of block RAMs, larger devices have hundreds, and the largest, the XC5VSX240T, has 1032. Because many designs do not require all of these block RAMs, this paper explores alternate uses for these functional blocks.
  • Peter Alfke
  • 2006
Summary form only given. This tutorial describes the why and how of the new 65-nm families of Virtex-5 FPGAs. It describes several aspects of the technology that affect speed, density, and power consumption. The basic device structure and package design have a strong impact on pc-board signal integrity and supply decoupling requirements. Various new or(More)