Peruvemba Balasubramanian

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The desire for higher performance and higher resolution continuously increases the pixel update rates needed in high performance graphics systems. The increasing density of memory chips on the other hand reduces the pixel update rate that can be provided by the frame buffer. We present the design of a VLSI chip and a graphics system that can sustain(More)
Error resiliency, which signifies the capability of a circuit to tolerate errors and produce correct outputs, assumes greater significance for digital design in the nanoscale regime due to the relentless miniaturization of semiconductor devices. In this context, the self-timed design paradigm forms an attractive and viable alternative for the VLSI design(More)
—Dynamic CMOS based transistor level designs of incrementer/decrementer circuit is presented in this work. The design of a new 8-bit decision module is first described. This is followed by elucidation of an original cascading architecture to realize larger size incrementer/decrementer circuits. From SPICE simulations corresponding to a 0.25µ µ µ µm CMOS(More)
– A novel circuit topology for the CMOS based Incrementer/Decrementer circuit is presented in this paper. The design methodology is extensively based on Domino logic and it utilizes a simple two level look-ahead structure. The highly parallel, regular structure of the proposed 8-bit decision module (DM) macro cell makes this design, especially advantageous(More)
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