Per Stenström

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The worst-case execution-time problem - overview of methods and survey of tools

Reinhard Wilhelm, Jakob Engblom, +12 authors Per Stenström
ACM Trans. Embedded Comput. Syst.
2008

The determination of upper bounds on execution times, commonly called worst-case execution times (WCETs), is a necessary step in the development and validation process for hard real-time systems.… (More)

SimICS/Sun4m: A Virtual Workstation

Peter S. Magnusson, Fredrik Larsson, +7 authors Håkan Grahn
USENIX Annual Technical Conference
1998

System level simulators allow computer architects and system software designers to recreate an accurate and complete replica of the program behavior of a target system, regardless of the… (More)

Timing Anomalies in Dynamically Scheduled Microprocessors

Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wrong in dynamically… (More)

A robust main-memory compression scheme

Magnus Ekman, Per Stenström
32nd International Symposium on Computer…
2005

Lossless data compression techniques can potentially free up more than 50% of the memory resources. However, previously proposed schemes suffer from high access costs. The proposed main-memory… (More)

An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors

Haakon Dybdahl, Per Stenström
IEEE 13th International Symposium on High…
2007

The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the capacity of shared… (More)

SC2: A statistical compression cache scheme

Angelos Arelakis, Per Stenström
ACM/IEEE 41st International Symposium on Computer…
2014

Low utilization of on-chip cache capacity limits performance and wastes energy because of the long latency, limited bandwidth, and energy consumption associated with off-chip memory accesses. Value… (More)

A Prefetching Technique for Irregular Accesses to Linked Data Structures

Magnus Karlsson, Fredrik Dahlgren, Per Stenström
HPCA
2000

Prefetching offers the potential to improve the performance of linked data structure (LDS) traversals. However, previously proposed prefetching methods only work well when there is enough work… (More)

Sequential Hardware Prefetching in Shared-Memory Multiprocessors

Fredrik Dahlgren, Michel Dubois, Per Stenström
IEEE Trans. Parallel Distrib. Syst.
1995

To offset the effect of read miss penalties on processor utilization in shared-memory multiprocessors, several softwareand hardware-based data prefetching schemes have been proposed. A major… (More)

Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors

Fredrik Dahlgren, Michel Dubois, Per Stenström
International Conference on Parallel Processing…
1993

To offset the effect of read miss penalties on processor utilization in shared-memory multiprocessors, several software- and hardware-based data prefetching schemes have been proposed. A major… (More)

Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms

Abstract: This paper considers program modules, e.g. procedures, functions, and methods as the basic method to exploit speculative parallelism in existing codes. We analyze how much inherent and… (More)

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