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- Reinhard Wilhelm, Jakob Engblom, +12 authors Per Stenström
- ACM Trans. Embedded Comput. Syst.
- 2008
The determination of upper bounds on execution times, commonly called worst-case execution times (WCETs), is a necessary step in the development and validation process for hard real-time systems.… (More)
- Thomas Lundqvist, Per Stenström
- RTSS
- 1999
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wrong in dynamically… (More)
- Per Stenström, Truman Joe, Anoop Gupta
- ISCA
- 1992
Two interesting variations of large-scale shared-memory machines that have recently emerged are <italic>cache-coherent non-uniform-memory-access</italic> machines (CC-NUMA) and <italic>cache-only… (More)
- Peter S. Magnusson, Fredrik Larsson, +7 authors Håkan Grahn
- USENIX Annual Technical Conference
- 1998
System level simulators allow computer architects and system software designers to recreate an accurate and complete replica of the program behavior of a target system, regardless of the… (More)
- Fredrik Dahlgren, Michel Dubois, Per Stenström
- 1993 International Conference on Parallel…
- 1993
To offset the effect of read miss penalties on processor utilization in shared-memory multiprocessors, several software- and hardware-based data prefetching schemes have been proposed. A major… (More)
- Magnus Ekman, Per Stenström
- 32nd International Symposium on Computer…
- 2005
Lossless data compression techniques can potentially free up more than 50% of the memory resources. However, previously proposed schemes suffer from high access costs. The proposed main-memory… (More)
- Haakon Dybdahl, Per Stenström
- 2007 IEEE 13th International Symposium on High…
- 2007
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the capacity of shared… (More)
- Fredrik Dahlgren, Michel Dubois, Per Stenström
- IEEE Trans. Parallel Distrib. Syst.
- 1995
To offset the effect of read miss penalties on processor utilization in shared-memory multiprocessors, several softwareand hardware-based data prefetching schemes have been proposed. A major… (More)
- Per Stenström, Mats Brorsson, Lars Sandberg
- ISCA
- 1993
Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a write-invalidate protocol result in invalidation actions that could be eliminated. For this type… (More)
- Magnus Karlsson, Fredrik Dahlgren, Per Stenström
- HPCA
- 2000
Prefetching offers the potential to improve the performance of linked data structure (LDS) traversals. However, previously proposed prefetching methods only work well when there is enough work… (More)