Peiyuan Wan

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A 1.2 V 12-bit 150 MS/s pipelined ADC with low-gain op-amps (DC gain ≈15 dB) is fabricated in a 65-nm CMOS process. The proposed 5-transistor single stage op-amp enables simple analog circuit to achieve low power and high speed. Digital background calibration technique is exploited to compensate the inter-stage gain error, capacitor mismatch and(More)
Power consumption is a key issue of smart card whose power is supplied by induced currents. This paper has described the principle of the clock gating technology which is used to optimize power consumption of the smart card in RTL level. It turns out that the total power consumption has been reduced by 40% using the proposed method, without obvious increase(More)
Frequency compensation of active-RC elliptic filter is enabled for the first time by employing a derivative-free architecture. In conjunction with a built-in automatic unity-gain band-width (&#x03C9;<inf>u</inf>) tracking scheme, the prototype 4th-order active-RC elliptic low-pass filter (LPF) measures a digitally programmable bandwidth of 14&#x2013;23 MHz,(More)
The design of a third-order single-bit discrete-time &#x03A3;&#x0394; modulator for low-power energy meter application is presented. The modulator employs an input feed-forward topology in order to reduce internal signal swings, thus relaxes the linearity and slew rate requirements on amplifiers. A partially switched amplifier is utilized in the first(More)
Conversion from dc to the 10th Nyquist band is enabled in a SHA-less, 10-b, 100-MS/s pipelined ADC by digitally calibrating the clock skew in the 3.5-b front-end stage. Architectural redundancy of pipelined ADC is exploited to extract skew information from the first-stage residue output with two out-of-range comparators and some simple digital logic; a(More)
This paper presents an interface readout circuit for Micromachined capacitive accelerometer. An analog closed-loop switched-capacitor (SC) interface circuit is proposed to achieve high linearity and large dynamic range of the sensor. Correlated double sampling (CDS) technique is used in SC circuits to minimize offset and 1/f noise of the amplifier. The(More)
In this Paper, a fractional-N frequency synthesizer fabricated in a 0.18µm process is designed for a FSK transceiver. The precision of the charge pump can be improved by exploiting the op amplifier. Based on capacitance multiplication technique, the area of loop filter is reduced. The fractional-N divider function is realized by the sigma delta modulator.(More)
This paper presents the design and simulation of a novel acceleration sensor with high accuracy and overload ability. A super-stable structure with quad-beams, which has a highly symmetric structure has been designed, and this helps to eliminate the errors caused by the change of the dimensions and position of the piezoresistors in the structure. At the(More)