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We present an ordered tree, O-tree, structure to represent non-slicing floor-plans. The O-tree uses only n (2 + rig nl) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both x and y direction. For each admissible placement, we can find an O-tree representation. We show that the number of possible… (More)

—We present an ordered tree (O tree) structure to represent nonslicing floorplans. The O tree uses only (2 + lg) bits for a floorplan of rectangular blocks. We define an admissible placement as a compacted placement in both and directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree… (More)

<italic>With the recent advent of deep sub-micron technology and new packaging schemes such as Multi-Chip Modules(MCMs), integrated circuit components are often not rectangular. Most existing block placement approaches, however, only deal with rectangular blocks, resulting in inefficient area utilization. New approaches which can handle arbitrarily shaped… (More)

We propose an iterative optimization approach for mixedmacro-cell and standard-cell placement, which minimizes the chipsize and interconnection wire length at the same time. We present abranch-and-bound algorithm which efficiently searches for the optimalsolution by evaluating all of the possible configurations on theselected cluster to minimize the gap… (More)

- Alex Gantman, Pei-Ning Guo, James Lewis, Fakhruddin Rashid
- 1998

We evaluate the options available to the designers of schedulers or real-time tasks in distributed systems. We also present a select subset of scheduling algorithms ranging from the classic Rate Monotonic Scheduling algorithm to the recent Real Time Self Adjusting Dynamic scheduling algorithm. Each algorithm is evaluated on the design choices made and their… (More)

In this paper, we present a physical retiming algorithm for sequential circuits implemented in field programmable gate arrays (FPGAs). This algorithm can speed up the sequential circuits by reducing delay of all critical paths with negative slacks. By taking advantage of the physical information provided by placed circuits, this algorithm integrates two… (More)

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