In this paper, we present a new global router, NTHU-Route, for modern designs. NTHU-Route is based on iterative rip-ups and reroutes, and several techniques are proposed to enhance our global router. These techniques include (1) a history based cost function which helps to distribute overflow during iterative rip-ups and reroutes, (2) an adaptive… (More)
Index Terms—Global router.
In routing, finding a rectilinear Steiner minimal tree (RSMT) is a fundamental problem. Today's design often contains rectilinear obstacles, like macro cells, IP blocks, and pre-routed nets. Therefore obstacle-avoiding RSMT (OARSMT) construction becomes a very practical problem. In this paper we present a fast and stable algorithm for this problem. We use a… (More)
The recent TAU computer-aided design (CAD) contest has aimed to seek novel ideas for accurate and fast clock network pessimism removal (CNPR). Unnecessary pessimism forces the static-timing analysis (STA) tool to report worse violation than the true timing properties owned by physical circuits, thereby misleading signoff timing into a lower clock frequency… (More)
As an important step in PCB design, the escape routing problem has been extensively studied in literature. However, few studies have been done on the escape routing of differential pairs. In this paper, we study the differential pair escape routing problem and propose two algorithms. The first one computes the optimal routing for a single differential pair… (More)
Common-path-pessimism removal (CPPR) is a pivotal step to achieve accurate timing signoff. Unnecessary pessimism might arise quality-of-result (QoR) concerns such as reporting worse violations than the true timing properties owned by the physical circuit. In other words, signoff timing report will conclude a lower clock frequency at which circuits can… (More)
Grid-based maze routing is a fundamental problem in electronic-design-automation (EDA) domain. A core primitive deals with a large query set about route connectivity subject to incremental changes on grid graph. Existing approaches pertain to batch processing, where each route query is independently and repeatedly solved by a routing procedure. Few… (More)
Timing closure, which is to meet the design's timing constraints, is a key problem in the physical design flow. During the timing optimization process, buffers can be used to speedup the circuit or serve as delay elements. In this paper, we study the hold-violation removal problem for today's industrial designs. Discrete buffers, accurate timing… (More)