Payman Behnam

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Arithmetic circuits require a verification process to prove that the gate level circuit is functionally equivalent to a high level specification or not. Furthermore, if two models are not equivalent, we need to automatically localize bugs and correct them with minimum user intervention. This paper presents a formal technique to verify and debug arithmetic(More)
In this paper, we present an efficient formal approach to check the equivalence of synthesized Register Transfer Level (RTL) against the high level specification in the presence of pipelining transformations. With the proposed equivalence checking method, fault tolerance issues when some faults happen in the designs can be formally analyzed. Equivalence(More)
Long test application time for a System on Chip (SoC) is a major problem in digital design testing. This problem mostly originates from large test data. High volume test data not only increases required ATE memory and bandwidth, but also increases test time. Test compression reduces test data volume without any impact on its coverage. This work proposes two(More)