Payam M. Farahabadi

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This paper presents a 60 GHz power amplifier utilizing a novel technique to achieve high efficiency at high output power levels. The proposed topology provides the capability of dual mode operation. The output power of a conventional class A power amplifier will be combined with the power provided by an amplifier operating at a different class to achieve(More)
This paper presents a compact 60 GHz power amplifier utilizing a novel 4-way multi-conductor power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area of 0.025 mm<sup>2</sup> with the advantage of lower insertion loss and higher efficiency compared(More)
in this paper, a low phase noise cross-coupled differential voltage controlled oscillator is designed in 0.13-&#x00B5;m CMOS for use in 60 GHz applications. Using a tuned output buffer, the single-ended output voltage of 1 Vp-p is provided into a 100-fF capacitive load. Measured phase noise below &#x2212;96 dBc/Hz at a 1-MHz offset is achieved, using an(More)
In this paper a low power design for CMOS ring oscillator is proposed and analyzed for power consumption. The proposed design is compared with an existing design. the simulation is done on Cadence virtuoso tool at 180nm CMOS technology and the results are analyzed for power consumption. The proposed ring oscillator circuit uses positive feedback in its(More)
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