Pawandip Kaur

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Reversible logic gates are in demand for the upcoming future computing technologies. Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design. The paper proposes the design of full Adder/Subtractor circuit using fault tolerant reversible logic gates. The design can work singly as a(More)
AbstractLow-Density Parity-Check (LDPC) codes are one of the most promising error-correcting codes approaching Shannon capacity and have been adopted in many applications. These codes offer huge advantages in terms of coding gain, throughput and power dissipation. Error correction algorithms are often implemented in hardware for fast processing to meet the(More)
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